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authorMiodrag Milanović <mmicko@gmail.com>2022-10-10 16:29:27 +0200
committerGitHub <noreply@github.com>2022-10-10 16:29:27 +0200
commite8ce9442a6a74621e06f30370c75390978c07cc8 (patch)
treef1d4417d1c6e82586fccdd7e3abb8c05a9daf686 /frontends
parentd68013811f316f3940110fde8435141279e6db5a (diff)
parentd29606532a15ae8e0c8d6c3591ccb36652d7339b (diff)
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Merge pull request #3452 from ALGCDG/master
Add BLIF names command input plane size check
Diffstat (limited to 'frontends')
-rw-r--r--frontends/blif/blifparse.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 73d1f0ea7..fe4c9078a 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -21,6 +21,8 @@
YOSYS_NAMESPACE_BEGIN
+const int lut_input_plane_limit = 12;
+
static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
{
string strbuf;
@@ -513,6 +515,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
sopmode = -1;
lastcell = sopcell;
}
+ else if (input_sig.size() > lut_input_plane_limit)
+ {
+ err_reason = stringf("names' input plane must have fewer than %d signals.", lut_input_plane_limit + 1);
+ goto error_with_reason;
+ }
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
@@ -576,7 +583,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (lutptr)
{
- if (input_len > 12)
+ if (input_len > lut_input_plane_limit)
goto error;
for (int i = 0; i < (1 << input_len); i++) {