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authorEddie Hung <eddie@fpgeh.com>2019-06-28 11:09:42 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-28 11:09:42 -0700
commit4ef26d4755d355e562a173c86d3eace100a266fe (patch)
tree6d331a5b3fa83d9072c25f7825cacb4e3d30cea5 /kernel/celltypes.h
parent1c79a32276ef4ae3601cb75e0ab05ba1afe4d385 (diff)
parentda5f83039527bf50af001671744f351988c3261a (diff)
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Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'kernel/celltypes.h')
-rw-r--r--kernel/celltypes.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 4e91eddda..758661c02 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -246,24 +246,24 @@ struct CellTypes
cell_types.clear();
}
- bool cell_known(RTLIL::IdString type)
+ bool cell_known(RTLIL::IdString type) const
{
return cell_types.count(type) != 0;
}
- bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
+ bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.outputs.count(port) != 0;
}
- bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
+ bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.inputs.count(port) != 0;
}
- bool cell_evaluable(RTLIL::IdString type)
+ bool cell_evaluable(RTLIL::IdString type) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.is_evaluable;
@@ -482,4 +482,3 @@ extern CellTypes yosys_celltypes;
YOSYS_NAMESPACE_END
#endif
-