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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 16:48:46 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 02:07:25 +0200 |
| commit | ff9713dd86cb6390f30392580e665095055a867c (patch) | |
| tree | 3cf9283d25bda9068970b8ee311765201ec93387 /kernel/mem.h | |
| parent | 95a39d342584fc9f98c57550aa7fba9e4652067b (diff) | |
| download | yosys-ff9713dd86cb6390f30392580e665095055a867c.tar.gz yosys-ff9713dd86cb6390f30392580e665095055a867c.tar.bz2 yosys-ff9713dd86cb6390f30392580e665095055a867c.zip | |
kernel/mem: Add model for wide ports.
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper. Subsequent commits will gradually
add wide port support to various yosys passes.
Diffstat (limited to 'kernel/mem.h')
| -rw-r--r-- | kernel/mem.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/mem.h b/kernel/mem.h index af06e970a..e0d8c277f 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -29,6 +29,7 @@ struct MemRd { bool removed; dict<IdString, Const> attributes; Cell *cell; + int wide_log2; bool clk_enable, clk_polarity; bool transparent; SigSpec clk, en, addr, data; @@ -39,6 +40,7 @@ struct MemWr { bool removed; dict<IdString, Const> attributes; Cell *cell; + int wide_log2; bool clk_enable, clk_polarity; std::vector<bool> priority_mask; SigSpec clk, en, addr, data; |