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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
| commit | 307dc55d65f9b9c07c10f6043ce0f165aac3852e (patch) | |
| tree | 3c48790ce444bc2de95d20b01181f6d871e53fbb /kernel/rtlil.cc | |
| parent | 85303334396904edfa0d77852b77c64870468f79 (diff) | |
| parent | 8a66bd30c67c753149a195b951a3191d8e5e3304 (diff) | |
| download | yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.gz yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.bz2 yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.zip | |
Merge branch 'ChipScan-master'
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f3522e30b..9539861cd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1636,18 +1636,19 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth } #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->setPort("\\A", sig_a); \ cell->setPort("\\Y", sig_y); \ + cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_y, is_signed); \ + add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Not, sig_a.size(), "$not") |