diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-06-17 13:46:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-17 13:50:09 +0200 |
| commit | 52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e (patch) | |
| tree | 59a78b1ea866b90e23c757bdba2c5c2680b9d636 /kernel/rtlil.cc | |
| parent | c3365034e9db8b6450db578daefd860276d5071f (diff) | |
| download | yosys-52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e.tar.gz yosys-52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e.tar.bz2 yosys-52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e.zip | |
Added $sop cell type and "abc -sop"
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a706491e8..3b1df4406 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -845,6 +845,15 @@ namespace { return; } + if (cell->type == "$sop") { + param("\\DEPTH"); + param("\\TABLE"); + port("\\A", param("\\WIDTH")); + port("\\Y", 1); + check_expected(); + return; + } + if (cell->type == "$sr") { param_bool("\\SET_POLARITY"); param_bool("\\CLR_POLARITY"); |