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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
| commit | bdc316db50cd8b68ef096386a89c1b38793784e1 (patch) | |
| tree | 507341053afa28df1a753ef9de33c3d096683720 /kernel/rtlil.cc | |
| parent | 2733994aeba0879533cc1a871aae84497b32ff9e (diff) | |
| download | yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.gz yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.bz2 yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.zip | |
Added $anyseq cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b0cda67b4..66bbf0427 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1037,7 +1037,7 @@ namespace { return; } - if (cell->type == "$anyconst") { + if (cell->type.in("$anyconst", "$anyseq")) { port("\\Y", param("\\WIDTH")); check_expected(); return; @@ -2009,6 +2009,15 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width) return sig; } +RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, width); + Cell *cell = addCell(name, "$anyseq"); + cell->setParam("\\WIDTH", width); + cell->setPort("\\Y", sig); + return sig; +} + RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name) { RTLIL::SigSpec sig = addWire(NEW_ID); |