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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-30 01:37:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-30 01:37:59 +0200 |
| commit | caa274ada6f2f35119cff943d0e9ed05dfaaeec7 (patch) | |
| tree | 14562590d3f49ce6379d1426d15b130c8668860c /kernel/rtlil.cc | |
| parent | df0163cd2b0dfd7c825f13ecb1c22f4f4d494a3b (diff) | |
| download | yosys-caa274ada6f2f35119cff943d0e9ed05dfaaeec7.tar.gz yosys-caa274ada6f2f35119cff943d0e9ed05dfaaeec7.tar.bz2 yosys-caa274ada6f2f35119cff943d0e9ed05dfaaeec7.zip | |
Added design->rename(module, new_name)
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7cd2dd4bb..cc7b1a7b8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -444,6 +444,13 @@ void RTLIL::Design::remove(RTLIL::Module *module) delete module; } +void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name) +{ + modules_.erase(module->name); + module->name = new_name; + add(module); +} + void RTLIL::Design::sort() { scratchpad.sort(); |