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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:10 -0700 |
| commit | cdbcd2efbdc7980aaad95744464c17553d782cd0 (patch) | |
| tree | 2c911e5c56f00545d217d246a94d12d4dd96a92a /kernel/rtlil.cc | |
| parent | f374e0ab7e9a91fa86814b0f750660e92ed16ae6 (diff) | |
| parent | b77322034c9234a8c24c6f53ed028fe29737b6b4 (diff) | |
| download | yosys-cdbcd2efbdc7980aaad95744464c17553d782cd0.tar.gz yosys-cdbcd2efbdc7980aaad95744464c17553d782cd0.tar.bz2 yosys-cdbcd2efbdc7980aaad95744464c17553d782cd0.zip | |
Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 94dbf31c0..a5fbfeda4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3438,7 +3438,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) if (width_ < width) { RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; - if (!is_signed) + if (padding != RTLIL::State::Sx && !is_signed) padding = RTLIL::State::S0; while (width_ < width) append(padding); |