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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 04:46:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 04:46:36 +0200 |
| commit | 22ede43b3f5016784b2e22c0ea95b7f718d7598e (patch) | |
| tree | dfa6d5c20d3efa5dff08e19f7a9c8b3a6a5a5109 /kernel/rtlil.h | |
| parent | 3a2c5357771df05f80bff55e8ab3e467308c57d1 (diff) | |
| download | yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.tar.gz yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.tar.bz2 yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.zip | |
Small changes regarding cover() and check() in SigSpec
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c25f71855..68eee46ea 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -599,7 +599,11 @@ public: operator std::vector<RTLIL::SigChunk>() const { return chunks(); } operator std::vector<RTLIL::SigBit>() const { return bits(); } +#ifndef NDEBUG void check() const; +#else + inline void check() const { } +#endif }; inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { |