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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:15:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch) | |
| tree | 27801c4b0171a2491ff6817ebb6d2a1d1484c086 /kernel/rtlil.h | |
| parent | 16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff) | |
| download | yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.gz yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.bz2 yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.zip | |
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7fb416f1f..88ed2f6a2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -560,8 +560,8 @@ public: }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { - assert(sig.__width == 1 && sig.__chunks.size() == 1); - *this = SigBit(sig.__chunks[0]); + assert(sig.size() == 1 && sig.chunks().size() == 1); + *this = SigBit(sig.chunks()[0]); } struct RTLIL::CaseRule { |