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authorwhitequark <whitequark@whitequark.org>2020-05-28 09:40:49 +0000
committerGitHub <noreply@github.com>2020-05-28 09:40:49 +0000
commit8a44a46806cc2246eea9668bd400dc4b37a38065 (patch)
tree8b7694cde4e61c45e817aa52f3aab615365c8c5c /kernel/rtlil.h
parent5b62dbb0af0400146c9fc625d8b37554d04e81fc (diff)
parent17b5f23f20d6cadc8ce6220e457880720aae4866 (diff)
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Merge pull request #2086 from rswarbrick/sigbit
Use default copy constructor for RTLIL::SigBit
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r--kernel/rtlil.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 10bfc13f2..96b10bbd6 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -721,7 +721,7 @@ struct RTLIL::SigBit
SigBit(const RTLIL::SigChunk &chunk);
SigBit(const RTLIL::SigChunk &chunk, int index);
SigBit(const RTLIL::SigSpec &sig);
- SigBit(const RTLIL::SigBit &sigbit);
+ SigBit(const RTLIL::SigBit &sigbit) = default;
RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
bool operator <(const RTLIL::SigBit &other) const;
@@ -1494,7 +1494,6 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
-inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; }
inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
if (wire == other.wire)