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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-07 18:17:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-07 18:17:10 +0100 |
| commit | 947bd9b96bb978e204275d6fbbc9ce9ff6eda28c (patch) | |
| tree | c9f0f53390c6fdfba52d26a3571d761ef28449f9 /kernel/rtlil.h | |
| parent | 0e1661f84e99f1d4a487e7a432b05a6cb2071714 (diff) | |
| download | yosys-947bd9b96bb978e204275d6fbbc9ce9ff6eda28c.tar.gz yosys-947bd9b96bb978e204275d6fbbc9ce9ff6eda28c.tar.bz2 yosys-947bd9b96bb978e204275d6fbbc9ce9ff6eda28c.zip | |
Renamed extend_un0() to extend_u0() and use it in genrtlil
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 376a09abf..7628bf0a8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -342,7 +342,7 @@ struct RTLIL::SigSpec { void append(const RTLIL::SigSpec &signal); bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false); void extend(int width, bool is_signed = false); - void extend_un0(int width, bool is_signed = false); + void extend_u0(int width, bool is_signed = false); void check() const; bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; |