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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-02 22:49:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-02 22:49:24 +0200 |
| commit | da360771a193707b59eac9b95b3bfe1652a057aa (patch) | |
| tree | 8f09645fbab743bfe8b0246584d29b007f674a70 /kernel/yosys.cc | |
| parent | c38283dbd033ba95554600bbaa850de707ab2a78 (diff) | |
| download | yosys-da360771a193707b59eac9b95b3bfe1652a057aa.tar.gz yosys-da360771a193707b59eac9b95b3bfe1652a057aa.tar.bz2 yosys-da360771a193707b59eac9b95b3bfe1652a057aa.zip | |
Create a default selection stack in RTLIL::Design::Design()
Diffstat (limited to 'kernel/yosys.cc')
| -rw-r--r-- | kernel/yosys.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7b8173b6a..0ecb4cdaf 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire) void yosys_setup() { Pass::init_register(); - yosys_design = new RTLIL::Design; - yosys_design->selection_stack.push_back(RTLIL::Selection()); log_push(); } |