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authorClifford Wolf <clifford@clifford.at>2014-01-28 06:55:47 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-28 06:55:47 +0100
commit2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0 (patch)
tree83a3e52f3a46f2db264106798e416da63e7ae743 /manual/CHAPTER_Eval/openmsp430.prj
parent842ca2f011a6030faccc690986accb0ca8035ec8 (diff)
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+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v"