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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 00:21:46 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-08 20:16:29 +0100 |
| commit | 4e03865d5bf3fafe0bd3735c88431675d53d2663 (patch) | |
| tree | 7ef637bd0526b498d32386bc1c79c671a02af7f0 /manual/CHAPTER_Overview.tex | |
| parent | c00a29296c8d3446c7cfe253080c7e33358219b0 (diff) | |
| download | yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.gz yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.bz2 yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.zip | |
Add support for memory writes in processes.
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 83db5aac7..50a56137c 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -350,8 +350,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or -more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type), zero or +more assignments (RTLIL::SigSig), and zero or more memory writes (RTLIL::MemWriteAction). +The {\tt always} synchronization condition is used to break combinatorial loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) |