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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
| commit | d938ce7ab6df091e0edd40f85f08fcd5458d9d6d (patch) | |
| tree | 1e7f17e720b7ab491cfd1defebef35f07dfb5de1 /manual/CHAPTER_Overview.tex | |
| parent | 23bb77867f56e966195d99d1d89b45d510d0b92d (diff) | |
| parent | e5eb3d2c8ace00aeedec410d17a4972a76782089 (diff) | |
| download | yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.gz yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.bz2 yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 964875d57..2feb0f1cb 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -428,8 +428,8 @@ memory object has the following properties: All read accesses to the memory are transformed to {\tt \$memrd} cells and all write accesses to {\tt \$memwr} cells by the language frontend. These cells consist of independent read- and write-ports -to the memory. The \B{MEMID} parameter on these cells is used to link them together and to the -RTLIL::Memory object they belong to. +to the memory. Memory initialization is transformed to {\tt \$meminit} cells by the language frontend. +The \B{MEMID} parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to. The rationale behind using separate cells for the individual ports versus creating a large multiport memory cell right in the language frontend is that |