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authorClifford Wolf <clifford@clifford.at>2014-09-06 11:46:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-06 11:46:44 +0200
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Merge branch 'master' of github.com:cliffordwolf/yosys
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@@ -32,7 +32,7 @@ the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional
mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can
-for example be usefull if the target architecture supports hardware multipliers for
+for example be useful if the target architecture supports hardware multipliers for
certain bit-widths but not for others.
A usual synthesis flow would first use the {\tt techmap} pass to directly map