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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-08 23:23:03 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-09 00:56:14 +0100 |
| commit | 1184a7f3b41f9044b603406c914bf43ab1808b28 (patch) | |
| tree | 27e0cc850ffd7e15fce407ae4e177a019d454e94 /manual/command-reference-manual.tex | |
| parent | d186ea7a2d74f859972746e03996e9eddc6a5157 (diff) | |
| download | yosys-1184a7f3b41f9044b603406c914bf43ab1808b28.tar.gz yosys-1184a7f3b41f9044b603406c914bf43ab1808b28.tar.bz2 yosys-1184a7f3b41f9044b603406c914bf43ab1808b28.zip | |
opt_mem_priority: Fix non-ascii char in help message.
This is a fixed version of #3072.
Diffstat (limited to 'manual/command-reference-manual.tex')
| -rw-r--r-- | manual/command-reference-manual.tex | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index d9a2f8dc1..28d2b6107 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -3163,7 +3163,7 @@ for removal of the read port. opt_mem_priority [selection] This pass detects cases where one memory write port has priority over another -even though they can never collide with each other — ie. there can never be +even though they can never collide with each other -- ie. there can never be a situation where a given memory bit is written by both ports at the same time, for example because of always-different addresses, or mutually exclusive enable signals. In such cases, the priority relation is removed. @@ -3661,11 +3661,6 @@ Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. - read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. - -Load the specified VHDL files. (Requires Verific.) - - read {-f|-F} <command-file> Load and execute the specified command file. (Requires Verific.) @@ -7480,11 +7475,6 @@ The macros SYNTHESIS and VERIFIC are defined implicitly. Like -sv, but define FORMAL instead of SYNTHESIS. - verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. - -Load the specified VHDL files into Verific. - - verific {-f|-F} <command-file> Load and execute the specified command file. |