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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-06 11:46:44 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-06 11:46:44 +0200 |
| commit | 34af6a130370671439da19ef55c2c45a35fd3ad0 (patch) | |
| tree | a822cd8d8cd5aa7f732dcb71fa20e391872e885a /manual/manual.tex | |
| parent | e1743b3bac8c86f3cf857892dabf66bec5573a7a (diff) | |
| parent | 652345c9cd41a6a93925477e44a6d7925b0d7584 (diff) | |
| download | yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.tar.gz yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.tar.bz2 yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'manual/manual.tex')
| -rw-r--r-- | manual/manual.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/manual.tex b/manual/manual.tex index c305ecb05..19d3b7b2f 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -144,7 +144,7 @@ Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when -testing new synthesis algorithms it might be neccessary to write a custom HDL +testing new synthesis algorithms it might be necessary to write a custom HDL synthesis tool or add new features to an existing one. It this cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. |