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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
| commit | 8fe0a961b306ef0c9c5de912833c6d92aed5f363 (patch) | |
| tree | 10325fb4b9a5d9a481177f0360fdbb8026e66367 /passes/cmds/add.cc | |
| parent | a20ed260e1b12da64bc4b40682c53145f6ffe827 (diff) | |
| parent | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (diff) | |
| download | yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.gz yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.bz2 yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.zip | |
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index cfccca966..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; |