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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
| commit | 1d88f1cf9f2088de7825f5292db5b40d4f73d036 (patch) | |
| tree | ef1eeba2dcddbe957dabb8147b2b81cdc0d2ecd3 /passes/cmds/connect.cc | |
| parent | 3cb61d03f8722fddfa14877accae1b3ca51e3926 (diff) | |
| download | yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.tar.gz yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.tar.bz2 yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.zip | |
Removed deprecated module->new_wire()
Diffstat (limited to 'passes/cmds/connect.cc')
| -rw-r--r-- | passes/cmds/connect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 7da2b9517..f99cb9b50 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width); for (auto &it : module->cells) for (auto &port : it.second->connections) |