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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:13:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:22:52 +0200 |
| commit | 1bf7a18fec76cf46a5b8710a75371e23b68d147d (patch) | |
| tree | ea445edda6c4bc0fa670effce4ef1b0eaf906258 /passes/hierarchy/hierarchy.cc | |
| parent | 746aac540b815099c6a63077010555369d7fdd5a (diff) | |
| download | yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.gz yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.bz2 yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.zip | |
Added module->ports
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 50b4989df..2f28afb25 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell wire->port_output = decl.output; } + mod->fixup_ports(); + for (auto ¶ : parameters) log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); |