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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
| commit | 0bc95f1e049afc35bb5ea30663b0a5725dfbf584 (patch) | |
| tree | 3a8641d3a9bb5794a24145ce368f3db7a3963709 /passes/hierarchy/submod.cc | |
| parent | 1565d1af69f552b790aa43fd6be194ee59ab76f3 (diff) | |
| download | yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.gz yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.bz2 yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.zip | |
Added "yosys -D" feature
Diffstat (limited to 'passes/hierarchy/submod.cc')
| -rw-r--r-- | passes/hierarchy/submod.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d4e8c96ca..9f312f82d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -298,7 +298,7 @@ struct SubmodPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n"); + log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_push(); std::string opt_name; @@ -321,7 +321,7 @@ struct SubmodPass : public Pass { if (opt_name.empty()) { Pass::call(design, "opt_clean"); - log_header("Continuing SUBMOD pass.\n"); + log_header(design, "Continuing SUBMOD pass.\n"); std::set<RTLIL::IdString> handled_modules; @@ -356,7 +356,7 @@ struct SubmodPass : public Pass { log("Nothing selected -> do nothing.\n"); else { Pass::call_on_module(design, module, "opt_clean"); - log_header("Continuing SUBMOD pass.\n"); + log_header(design, "Continuing SUBMOD pass.\n"); SubmodWorker worker(design, module, copy_mode, opt_name); } } |