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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
| commit | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (patch) | |
| tree | bcee5a22fc9ac7dca5b871ce667114e5f15d07d0 /passes/hierarchy/submod.cc | |
| parent | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (diff) | |
| download | yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.gz yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.bz2 yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.zip | |
Added module->design and cell->module, wire->module pointers
Diffstat (limited to 'passes/hierarchy/submod.cc')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 84c6b9161..d0c9f4b5a 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -105,7 +105,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; - design->modules_[new_mod->name] = new_mod; + design->add(new_mod); int port_counter = 1, auto_name_counter = 1; std::set<std::string> all_wire_names; |