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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 15:54:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 15:54:07 -0700 |
| commit | 3f677fb0db15f75d9655fe653f991c94e78a4a1f (patch) | |
| tree | 92433435d6b6f68ade5d8e6f8846ca0dbbb0895f /passes/pmgen/xilinx_dsp.cc | |
| parent | 6390c535ba70c0a4fe0cb08156fefa80fb621e47 (diff) | |
| download | yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.tar.gz yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.tar.bz2 yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.zip | |
Signed extension
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index a09f96a7f..a4602dd63 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -50,7 +50,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) if (st.ffA) { SigSpec D = st.ffA->getPort("\\D"); - cell->setPort("\\A", D.extend_u0(30)); + cell->setPort("\\A", D.extend_u0(30, true)); cell->setParam("\\AREG", State::S1); if (st.ffA->type == "$dff") cell->setPort("\\CEA2", State::S1); @@ -60,7 +60,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) } if (st.ffB) { SigSpec D = st.ffB->getPort("\\D"); - cell->setPort("\\B", D.extend_u0(18)); + cell->setPort("\\B", D.extend_u0(18, true)); cell->setParam("\\BREG", State::S1); if (st.ffB->type == "$dff") cell->setPort("\\CEB2", State::S1); |