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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:37:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:37:59 -0700 |
| commit | 80aec0f006b91b0163c8be94f2450223e6e97a52 (patch) | |
| tree | c52d47e482fe9c598450e97a6668afbab694e49b /passes/pmgen/xilinx_dsp.cc | |
| parent | 16316aa05d548c79fa1580defe71097efdeb78b9 (diff) | |
| download | yosys-80aec0f006b91b0163c8be94f2450223e6e97a52.tar.gz yosys-80aec0f006b91b0163c8be94f2450223e6e97a52.tar.bz2 yosys-80aec0f006b91b0163c8be94f2450223e6e97a52.zip | |
st.ffP from if to assert
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 17e05c39c..95105275b 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -59,7 +59,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); SigSpec &opmode = cell->connections_.at("\\OPMODE"); - if (st.ffP && st.postAddMux) { + if (st.postAddMux) { + log_assert(st.ffP); opmode[4] = st.postAddMux->getPort("\\S"); pm.autoremove(st.postAddMux); } |