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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 15:54:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 15:54:07 -0700 |
| commit | 3f677fb0db15f75d9655fe653f991c94e78a4a1f (patch) | |
| tree | 92433435d6b6f68ade5d8e6f8846ca0dbbb0895f /passes/pmgen/xilinx_dsp.pmg | |
| parent | 6390c535ba70c0a4fe0cb08156fefa80fb621e47 (diff) | |
| download | yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.tar.gz yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.tar.bz2 yosys-3f677fb0db15f75d9655fe653f991c94e78a4a1f.zip | |
Signed extension
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index ceed64b30..4b7bea308 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -9,10 +9,10 @@ endmatch match ffA select ffA->type.in($dff, $dffe) + select param(ffA, \CLK_POLARITY).as_bool() // select nusers(port(ffA, \Q)) == 2 - index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A) + index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25) // DSP48E1 does not support clock inversion - index <Const> param(ffA, \CLK_POLARITY).as_bool() === true optional endmatch @@ -23,9 +23,9 @@ endcode match ffB select ffB->type.in($dff, $dffe) + select param(ffB, \CLK_POLARITY).as_bool() // select nusers(port(ffB, \Q)) == 2 - index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B) - index <Const> param(ffB, \CLK_POLARITY).as_bool() === true + index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B) optional endmatch |