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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/sat/freduce.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/sat/freduce.cc')
| -rw-r--r-- | passes/sat/freduce.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index ac0415644..8cc59b291 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -714,7 +714,7 @@ struct FreduceWorker if (grp[i].inverted) { - if (inv_sig.width == 0) + if (inv_sig.__width == 0) { inv_sig = module->addWire(NEW_ID); |