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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 14:46:48 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 14:46:48 -0800 |
| commit | 0b308c68357cc85876c3c86d6e5ac8b9318329ca (patch) | |
| tree | fe86498552867fca4440d314280abc3a3a974c01 /passes/techmap/abc9_ops.cc | |
| parent | 5ebdc0f8e07989b79337ced0553bd28819a8cf3e (diff) | |
| download | yosys-0b308c68357cc85876c3c86d6e5ac8b9318329ca.tar.gz yosys-0b308c68357cc85876c3c86d6e5ac8b9318329ca.tar.bz2 yosys-0b308c68357cc85876c3c86d6e5ac8b9318329ca.zip | |
abc9_ops: -reintegrate to use derived_type for box_ports
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 2b4a5c802..7071f0de4 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -797,7 +797,7 @@ void reintegrate(RTLIL::Module *module) } int input_count = 0, output_count = 0; - for (const auto &port_name : box_ports.at(cell->type)) { + for (const auto &port_name : box_ports.at(derived_type)) { RTLIL::Wire *w = box_module->wire(port_name); log_assert(w); |