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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-16 12:43:17 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-16 12:43:17 +0100 |
| commit | 32f0296df1b97ff5b3bcc442ac38f27a786947d6 (patch) | |
| tree | 72ec224a90bb5a40e007a88fe37085dcc786a0e0 /passes/techmap/flowmap.cc | |
| parent | ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 (diff) | |
| parent | 51e4e29bb1f7c030b0cac351c522dc41f7587be2 (diff) | |
| download | yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.tar.gz yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.tar.bz2 yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'passes/techmap/flowmap.cc')
| -rw-r--r-- | passes/techmap/flowmap.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 5807178dd..a2ad87f7d 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -394,7 +394,7 @@ struct FlowGraph pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> edge_cut() { - pool<RTLIL::SigBit> x, xi; + pool<RTLIL::SigBit> x = {source}, xi; // X and X̅ in the paper NodePrime source_prime = {source, true}; pool<NodePrime> visited; @@ -437,6 +437,7 @@ struct FlowGraph for (auto collapsed_node : collapsed[sink]) xi.insert(collapsed_node); + log_assert(x[source] && !xi[source]); log_assert(!x[sink] && xi[sink]); return {x, xi}; } @@ -1050,7 +1051,7 @@ struct FlowmapWorker auto cut_inputs = cut_lut_at_gate(lut, lut_gate); pool<RTLIL::SigBit> gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second; - if (gate_inputs.empty() && (int)other_inputs.size() == order) + if (gate_inputs.empty() && (int)other_inputs.size() >= order) { if (debug_relax) log(" Breaking would result in a (k+1)-LUT.\n"); |