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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-21 11:25:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-21 11:25:36 +0200 |
| commit | 0a2d8db793fee47d8237c472c1d2d5ca4e21f865 (patch) | |
| tree | a1aefed72ac4291f41d77ea3fe651c500cebab35 /passes/techmap/techmap.cc | |
| parent | f3781f98db227f160e08b2fc7cf8c61f663a56c9 (diff) | |
| parent | 7c8de1dd180e4d6cf708700d73f29f3b581722ce (diff) | |
| download | yosys-0a2d8db793fee47d8237c472c1d2d5ca4e21f865.tar.gz yosys-0a2d8db793fee47d8237c472c1d2d5ca4e21f865.tar.bz2 yosys-0a2d8db793fee47d8237c472c1d2d5ca4e21f865.zip | |
Merge pull request #1392 from YosysHQ/eddie/fix1391
(* techmap_autopurge *) fixes when ports aren't consistently-sized
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cf40b2f17..1d0362ad6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -224,7 +224,7 @@ struct TechmapWorker for (auto bit : sigmaps.at(tpl)(it.second)) if (bit.wire != nullptr) - autopurge_tpl_bits.insert(it.second); + autopurge_tpl_bits.insert(bit); } } IdString w_name = it.second->name; @@ -359,6 +359,12 @@ struct TechmapWorker for (auto &attr : w->attributes) { if (attr.first == ID(src)) continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); module->connect(extra_connect); break; } |