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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
| commit | d938ce7ab6df091e0edd40f85f08fcd5458d9d6d (patch) | |
| tree | 1e7f17e720b7ab491cfd1defebef35f07dfb5de1 /techlibs/anlogic/Makefile.inc | |
| parent | 23bb77867f56e966195d99d1d89b45d510d0b92d (diff) | |
| parent | e5eb3d2c8ace00aeedec410d17a4972a76782089 (diff) | |
| download | yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.gz yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.bz2 yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 59be83fd0..f37b5e7e9 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -5,5 +5,6 @@ OBJS += techlibs/anlogic/anlogic_eqn.o $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) |