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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-18 14:38:44 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-18 14:38:44 +0800 |
| commit | 7854d5ba217788bb66881237feac8ba2748758b9 (patch) | |
| tree | dcc2e348e10f5792611c874cc2444fce02c260c5 /techlibs/anlogic/anlogic_determine_init.cc | |
| parent | 847fd360773d72933f1c728dba0755e0033350a6 (diff) | |
| download | yosys-7854d5ba217788bb66881237feac8ba2748758b9.tar.gz yosys-7854d5ba217788bb66881237feac8ba2748758b9.tar.bz2 yosys-7854d5ba217788bb66881237feac8ba2748758b9.zip | |
anlogic: fix dbits of Anlogic Eagle DRAM16X4
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/anlogic/anlogic_determine_init.cc')
0 files changed, 0 insertions, 0 deletions