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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
| commit | d938ce7ab6df091e0edd40f85f08fcd5458d9d6d (patch) | |
| tree | 1e7f17e720b7ab491cfd1defebef35f07dfb5de1 /techlibs/anlogic/drams.txt | |
| parent | 23bb77867f56e966195d99d1d89b45d510d0b92d (diff) | |
| parent | e5eb3d2c8ace00aeedec410d17a4972a76782089 (diff) | |
| download | yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.gz yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.bz2 yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/anlogic/drams.txt')
| -rw-r--r-- | techlibs/anlogic/drams.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt index 2bff14a03..eb94775ae 100644 --- a/techlibs/anlogic/drams.txt +++ b/techlibs/anlogic/drams.txt @@ -1,7 +1,7 @@ bram $__ANLOGIC_DRAM16X4 init 0 abits 4 - dbits 2 + dbits 4 groups 2 ports 1 1 wrmode 0 1 |