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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
| commit | 550310e2647c7aac1e49b79d9ff912436103062f (patch) | |
| tree | 7627eab28fcd68104522d1623108ebb478c9aa84 /techlibs/anlogic/lutrams_map.v | |
| parent | 22fe931c861aa3f557327baf9d12ec57006308d9 (diff) | |
| download | yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.gz yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.bz2 yosys-550310e2647c7aac1e49b79d9ff912436103062f.zip | |
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
Diffstat (limited to 'techlibs/anlogic/lutrams_map.v')
| -rw-r--r-- | techlibs/anlogic/lutrams_map.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/anlogic/lutrams_map.v b/techlibs/anlogic/lutrams_map.v new file mode 100644 index 000000000..5a464cafc --- /dev/null +++ b/techlibs/anlogic/lutrams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "lutram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |