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| author | whitequark <whitequark@whitequark.org> | 2020-01-02 21:06:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-02 21:06:17 +0000 |
| commit | f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (patch) | |
| tree | e7c5b19ffae2bfc40e682f696d2ae40513717ad7 /techlibs/anlogic/lutrams_map.v | |
| parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
| parent | 550310e2647c7aac1e49b79d9ff912436103062f (diff) | |
| download | yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.gz yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.bz2 yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.zip | |
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
Diffstat (limited to 'techlibs/anlogic/lutrams_map.v')
| -rw-r--r-- | techlibs/anlogic/lutrams_map.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/anlogic/lutrams_map.v b/techlibs/anlogic/lutrams_map.v new file mode 100644 index 000000000..5a464cafc --- /dev/null +++ b/techlibs/anlogic/lutrams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "lutram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |