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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:16:35 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:16:35 -0800 |
| commit | 728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6 (patch) | |
| tree | c24ccc8fabbe0dbf74f00278900b866d7e6e0b32 /techlibs/common/simcells.v | |
| parent | e1153031291275dc1c16445b1b2089ffd4335845 (diff) | |
| parent | d9fa4387c97745c558acdd8ea7f436917302796e (diff) | |
| download | yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.tar.gz yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.tar.bz2 yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.zip | |
Merge pull request #718 from whitequark/gate2lut
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 937512e7c..289673e82 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -465,7 +465,7 @@ endmodule //- //- $_SR_NP_ (S, R, Q) //- -//- A set-reset latch with negative polarity SET and positive polarioty RESET. +//- A set-reset latch with negative polarity SET and positive polarity RESET. //- //- Truth table: S R | Q //- -----+--- @@ -489,7 +489,7 @@ endmodule //- //- $_SR_PN_ (S, R, Q) //- -//- A set-reset latch with positive polarity SET and negative polarioty RESET. +//- A set-reset latch with positive polarity SET and negative polarity RESET. //- //- Truth table: S R | Q //- -----+--- |