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| author | whitequark <whitequark@whitequark.org> | 2019-08-09 17:10:46 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-09 17:10:46 +0000 |
| commit | 39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3 (patch) | |
| tree | bf00c07c3cc9d785331ef12392e85ae00b3b21d0 /techlibs/common/simlib.v | |
| parent | ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76 (diff) | |
| parent | 0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8 (diff) | |
| download | yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.tar.gz yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.tar.bz2 yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.zip | |
Merge pull request #1267 from whitequark/proc_prune-fix-1243
proc_prune: fix handling of exactly identical assigns
Diffstat (limited to 'techlibs/common/simlib.v')
0 files changed, 0 insertions, 0 deletions