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| author | Zachary Snow <zach@zachjs.com> | 2021-02-11 10:26:49 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-11 10:26:49 -0500 |
| commit | 73d611990d7f39b4e14ffc367c646686f0d2b209 (patch) | |
| tree | 6ed0d4b18195c987bef60a0134bf25514e4ab9ab /techlibs/common/simlib.v | |
| parent | c383d156e9015cde4718f3a6bc3371dc87c3e4fe (diff) | |
| parent | 1d5f3fe5064146955dafdabafe7180ff79c95d08 (diff) | |
| download | yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.gz yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.bz2 yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.zip | |
Merge pull request #2578 from zachjs/genblk-port
verlog: allow shadowing module ports within generate blocks
Diffstat (limited to 'techlibs/common/simlib.v')
0 files changed, 0 insertions, 0 deletions