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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-02 17:15:28 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-02 23:16:12 +0200 |
| commit | 71dfbf33b292b6920ff1bab308c0c10b737bf763 (patch) | |
| tree | 4e844cbe19ede678ee1efd0cf5a1581f2f9b0d23 /techlibs/common/synth.cc | |
| parent | 3a0aa9c6630c6e2bb2ffb2d7f5b4e3921316ba48 (diff) | |
| download | yosys-71dfbf33b292b6920ff1bab308c0c10b737bf763.tar.gz yosys-71dfbf33b292b6920ff1bab308c0c10b737bf763.tar.bz2 yosys-71dfbf33b292b6920ff1bab308c0c10b737bf763.zip | |
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
Diffstat (limited to 'techlibs/common/synth.cc')
| -rw-r--r-- | techlibs/common/synth.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 79e5933e0..63395c368 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -81,6 +81,11 @@ struct SynthPass : public ScriptPass log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of ABC\n"); log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -175,6 +180,10 @@ struct SynthPass : public ScriptPass flowmap = true; continue; } + if (args[argidx] == "-no-rw-check") { + memory_opts += " -no-rw-check"; + continue; + } break; } extra_args(args, argidx, design); |