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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-02 17:48:41 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-02 17:48:41 +0200 |
| commit | c38283dbd033ba95554600bbaa850de707ab2a78 (patch) | |
| tree | 26c4d56235b59a023c3cfdd6023014cc322c7509 /techlibs/common | |
| parent | acd7a99aef0f698580dc6a6d202a79f36fdf5360 (diff) | |
| download | yosys-c38283dbd033ba95554600bbaa850de707ab2a78.tar.gz yosys-c38283dbd033ba95554600bbaa850de707ab2a78.tar.bz2 yosys-c38283dbd033ba95554600bbaa850de707ab2a78.zip | |
Small bug fixes in $not, $neg, and $shiftx models
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 3c931c813..09ffa9a68 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -108,13 +108,12 @@ parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; output [Y_WIDTH-1:0] Y; -wire [Y_WIDTH-1:0] tmp; generate if (A_SIGNED) begin:BLOCK1 - assign tmp = $signed(A), Y = -tmp; + assign Y = -$signed(A); end else begin:BLOCK2 - assign tmp = A, Y = -tmp; + assign Y = -A; end endgenerate |