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authorEddie Hung <eddie@fpgeh.com>2019-10-04 17:27:05 -0700
committerEddie Hung <eddie@fpgeh.com>2019-10-04 17:27:05 -0700
commitd4212d128b5985cf09f5e7f14bc06e7323e644ac (patch)
tree2559c896b7cf787674e477feb3af4763cb6967f9 /techlibs/ecp5/brams_connect.py
parent7959e9d6b25d7afefded4b14e14ccf2b0b5af553 (diff)
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Use read_args for read_verilog
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