diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:27:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:27:05 -0700 |
| commit | d4212d128b5985cf09f5e7f14bc06e7323e644ac (patch) | |
| tree | 2559c896b7cf787674e477feb3af4763cb6967f9 /techlibs | |
| parent | 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 (diff) | |
| download | yosys-d4212d128b5985cf09f5e7f14bc06e7323e644ac.tar.gz yosys-d4212d128b5985cf09f5e7f14bc06e7323e644ac.tar.bz2 yosys-d4212d128b5985cf09f5e7f14bc06e7323e644ac.zip | |
Use read_args for read_verilog
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 16b607aac..caeeb3266 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass ff_map_file = "+/xilinx/xc7_ff_map.v"; if (check_label("begin")) { + std::string read_args; if (vpr) - run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); - else - run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); + read_args += " -D_EXPLICIT_CARRY"; + if (abc9) + read_args += " -D_ABC9"; + read_args += " -lib +/xilinx/cells_sim.v"; + run("read_verilog" + read_args); if (help_mode) run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); |