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-rw-r--r--techlibs/ecp5/synth_ecp5.cc1
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index e5c1f7550..aceb36abc 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -334,7 +334,6 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
if (abc9) {
- run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
std::string abc9_opts;
if (nowidelut)
abc9_opts += " -maxlut 4";