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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
commit | 5c89dead5f481edaccd46ebc0af907544c89654f (patch) | |
tree | c40306fef9c52f8065cf5f19b42f31b668b17526 /techlibs/ice40/abc9_hx.box | |
parent | 01866a79093092bc2f8a8b20376f6cb552f76f00 (diff) | |
parent | ce765aa4def09bd8b0161425ee40ee55f62e33ff (diff) | |
download | yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.gz yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.bz2 yosys-5c89dead5f481edaccd46ebc0af907544c89654f.zip |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/ice40/abc9_hx.box')
-rw-r--r-- | techlibs/ice40/abc9_hx.box | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box index 3ea70bc91..31e743669 100644 --- a/techlibs/ice40/abc9_hx.box +++ b/techlibs/ice40/abc9_hx.box @@ -1,13 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) -# Inputs: A B I0 I3 CI -# Outputs: O CO -# (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) -$__ICE40_CARRY_WRAPPER 1 1 5 2 -400 379 449 316 316 -259 231 - - 126 +# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve +# SB_LUT4+SB_CARRY) +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +$__ICE40_CARRY_WRAPPER 1 1 5 2 +#A B I0 I3 CI +400 379 449 316 316 # O +259 231 - - 126 # CO |