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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 23:07:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 23:07:16 -0700 |
| commit | 19b660ff6e8b493ff3de43ce59e393c56b9a6b3b (patch) | |
| tree | fcc2c58996d329bf79ce1a0e0b3b653a72c1dcf2 /techlibs/ice40/cells_sim.v | |
| parent | 0919f36b88bed88e6dbfa23381540dc8ee035962 (diff) | |
| download | yosys-19b660ff6e8b493ff3de43ce59e393c56b9a6b3b.tar.gz yosys-19b660ff6e8b493ff3de43ce59e393c56b9a6b3b.tar.bz2 yosys-19b660ff6e8b493ff3de43ce59e393c56b9a6b3b.zip | |
Fix SB_DFF comb model
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 1d104c5d7..c49b29ab3 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in always @(posedge C) Q <= D; `else - assign Q = D; + always @* Q = D; `endif endmodule |