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| author | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
| commit | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch) | |
| tree | 4780799b6c1dc1d150b80aa142e6c53e06760cb3 /techlibs/ice40/ice40_opt.cc | |
| parent | edff79a25a802e5b1816608b48e3ac335ad87147 (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2 yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip | |
Merge branch 'master' into xc7dsp
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index d5106b805..ea56d3f4d 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module) continue; } - if (cell->type == "$__ICE40_FULL_ADDER") + if (cell->type == "$__ICE40_CARRY_WRAPPER") { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; @@ -114,16 +114,17 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", + log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); + cell->unsetPort("\\I0"); + cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); cell->setParam("\\WIDTH", 4); } continue; |