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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 16:27:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 16:27:40 -0800 |
| commit | 3d9737c1bd05235b2c32fe9daaaa9004924a6018 (patch) | |
| tree | 36c965a05ad7e1afc7baf2cf7c46922be2bd1918 /techlibs/ice40 | |
| parent | cd093c00f84b44662a09d469c2b0d8ba6ecf6f6e (diff) | |
| parent | 5791c52e1b0c0e52299ee1c293a41d712d782422 (diff) | |
| download | yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.tar.gz yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.tar.bz2 yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 10 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 3 |
2 files changed, 10 insertions, 3 deletions
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index 3089d8932..c098736e9 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -78,10 +78,12 @@ struct Ice40FfinitPass : public Pass { continue; if (initbits.count(bit)) { - if (initbits.at(bit) != val) - log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n", + if (initbits.at(bit) != val) { + log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n", log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val), log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit))); + initbits.at(bit) = State::Sx; + } continue; } @@ -114,6 +116,10 @@ struct Ice40FfinitPass : public Pass { continue; State val = initbits.at(bit_q); + + if (val == State::Sx) + continue; + handled_initbits.insert(bit_q); log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type), diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 121bcff1f..d92e40726 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("memory_dff"); + run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first + run("wreduce t:$mul"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); |