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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-30 13:19:27 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-30 13:19:27 -0700 |
| commit | 58650ffe876d1caedd8ffc9b0207f5cf75eef97b (patch) | |
| tree | 5389584f1c3ad8c9e9003e78d4b6e22dca5e3a83 /techlibs/ice40 | |
| parent | 354ba5ba83f7b1fc3bb07aa6bf26dde7a00201d1 (diff) | |
| parent | e35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 (diff) | |
| download | yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.tar.gz yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.tar.bz2 yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 29 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 10 |
2 files changed, 25 insertions, 14 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 62a28364b..00843b97c 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -27,18 +27,27 @@ module SB_IO ( reg dout_q_0, dout_q_1; reg outena_q; + // IO tile generates a constant 1'b1 internally if global_cen is not connected + wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz; + reg clken_pulled_ri; + reg clken_pulled_ro; + generate if (!NEG_TRIGGER) begin - always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN; - always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN; - always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0; - always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1; - always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE; + always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled; + always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN; + always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN; + always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled; + always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0; + always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1; + always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE; end else begin - always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN; - always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN; - always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0; - always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1; - always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE; + always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled; + always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN; + always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN; + always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled; + always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0; + always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1; + always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE; end endgenerate always @* begin diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 8899bfcc4..5de33110a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -225,11 +225,13 @@ struct SynthIce40Pass : public ScriptPass run("proc"); } - if (flatten && check_label("flatten", "(unless -noflatten)")) + if (check_label("flatten", "(unless -noflatten)")) { - run("flatten"); - run("tribuf -logic"); - run("deminout"); + if (flatten) { + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } } if (check_label("coarse")) |