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| author | Aman Goel <amangoel@umich.edu> | 2018-07-18 11:34:18 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-18 11:34:18 -0400 |
| commit | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (patch) | |
| tree | 28501a5765389f8197211ca67845398a3da42d05 /techlibs/ice40 | |
| parent | f0b1ec3e9758582bc0215e646c331e45a4e2a824 (diff) | |
| parent | 65234d4b24edd1ec8ec5d41df2d56d76fa41dcc5 (diff) | |
| download | yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.tar.gz yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.tar.bz2 yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.zip | |
Merge pull request #2 from YosysHQ/master
Merging with official repo
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 45a02111f..9f73aeb07 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -657,7 +657,12 @@ module ICESTORM_LC ( parameter [0:0] SET_NORESET = 0; parameter [0:0] ASYNC_SR = 0; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; + parameter [0:0] CIN_CONST = 0; + parameter [0:0] CIN_SET = 0; + + wire mux_cin = CIN_CONST ? CIN_SET : CIN; + + assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; @@ -1226,4 +1231,3 @@ module SB_IO_OD ( endgenerate `endif endmodule - |